The present invention relates to a semiconductor device error evaluation support technique, and more particularly, it relates to a technique to calculate, as a function of neutron energy, a rate of error occurrence in the semiconductor device, the error being caused by neutrons.
In recent years, remarkable progress is made on high integration of semiconductor device such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). Concurrent with the high integration of semiconductor device in these years, a trend for reduction in size of a memory cell is in progress. Accordingly, electrostatic capacitance becomes smaller, and it is increasingly difficult to keep high reliability against soft errors, which are generally caused by alpha rays, neutron beams or the like (for example, see F. J. Ziegler, IBM J. Res. Develop., Vol. 40, No. 1, 1996, pp. 19-29, hereinafter referred to as “Non-patent Document 1”). Here, the term “soft error” means a phenomenon that information stored in a memory cell is inverted. For example, it indicates a phenomenon that electric charge generated in a semiconductor memory device due to alpha rays, neutron beams or the like is collected in a storage node (a diffusion layer part to hold data), under the influence of an electric field substantially associated with PN junction, and information “1” written in the memory cell is rewritten by information “zero”.
Soft errors are temporal non-destructive events, but there is also a concern for hard errors (destructive events) to increase concurrent with a finer structure and higher integration of the semiconductor device (for example, see IEEE Transactions on Nuclear Science, Vol. 45, No. 6, pp. 2492-2499 (1998), IEEE Transactions on Nuclear Science, Vol. 47, No. 6, pp. 2373-2379 (2000), and IEEE Transactions on Nuclear Science, Vol. 47, No. 6, pp. 2640-2647 (2000), which will be referred to as “Non-patent Documents 2, 3 and 4”, respectively). It is to be noted that an error (event) caused by the incidence of one particle, such as an ion and neutron, into the semiconductor device, is referred to as “SEE (Single Event Effect)”.
By the way, soft errors caused by alpha rays were recognized at the end 1970's. The alpha rays are emitted from radioactive isotopes such as uranium (U) and thorium (Th), which are contained in minute quantities in a wiring material or in a packaging material constituting the semiconductor device. In 1980's, following solutions were suggested in order to enhance resistivity against the soft errors caused by the alpha rays. With the following solutions, it is thought that almost all the soft error problems caused by the alpha rays have been solved.
Solution 1:
Highly purified Materials used for the semiconductor device.
Solution 2:
Shielding alpha rays from the packaging material such as a polyimide layer or the like.
Solution 3:
Increasing or keeping electrostatic capacitance of memory devices high enough.
Solution 4:
Contrive a well structure of the semiconductor device by installing a barrier layer or the like against generated carrier.
In the meantime, possibility of soft errors caused by cosmic ray neutrons was pointed out at the end 1970's around the same time when the soft errors caused by the alpha rays were found. A principle of the soft errors caused by cosmic ray neutrons will be explained in the following.
A neutron arriving to the ground is a secondary neutron with an extremely high energy at the order of several MeV to GeV, which has been generated by a reaction between the high-energy cosmic ray and atomic nucleus such as oxygen, contained in the air. FIG. 14 is an illustration to schematically explain the principle of the soft errors caused by the cosmic ray neutrons, and it shows a cross sectional structure of a general semiconductor device (DRAM).
As illustrated, when the cosmic ray neutron 1 with high energy comes into the semiconductor device, it enters an atomic nucleus of an atom constituting the semiconductor device with a certain probability. Then, within an extremely short period of time, a cascade of elastic scattering takes place between the cosmic ray neutron and intra-nucleus nucleons (neutron and proton), and as a result, a nucleon having sufficient kinetic energy against the nucleus potential is emitted out of the nucleus. After all the releasable nucleons have been emitted, other nucleons and leptons such as deuteron and helium “evaporate” out of the nucleus, using the sum of the remaining kinetic energy as excitation energy. The above serial processing is called as nuclear spallation reaction (1a). For example, a proton and secondary ions 2 having all the atomic numbers from alpha particle up to 29Si (in which 28Si spins out of the lattice position, keeping the neutron absorbed therein) are generated from 28Si atomic nucleus.
Next, the secondary ion 2 generates electron hole pairs 6a in the number corresponding to its energy, and simultaneously moves within the semiconductor device. When the secondary ion 2 passes through a storage node 3, which is a diffusion layer part holding data, an electric charge generated within the field outside the storage node 3 flows along the electric field. Therefore, the charge is collected into the storage node 3. An area to which the charge is collected in the storage node 3 is referred to as a charge collection area. It is to be noted here that the electric field includes a depletion layer 4 positioned outside the storage node 3, and an area 6 called funneling, positioned within the well area 5 including the storage node 3, the area 6 being generated by extension of the electric field of the depletion layer 4.
The semiconductor device as shown in FIG. 14 represents a DRAM where a capacitor 7 is added onto the storage node 3. In many cases, the DRAM has a triple well structure, in which a lower circumference of the storage node 3 (in general, it is n-type semiconductor) is covered with a well 5 being a semiconductor having opposite polarity, and the outside thereof is surrounded by a substrate 8 being a semiconductor having the same polarity as that of the storage node 3. In other words, PN junction is found on both sides, i.e., on the storage node 3 side and on the substrate 8 side, and when the secondary ion 2 penetrates into the storage node 3, the well 5 and the substrate 8, funneling extends also from the PN junction on the substrate 8 side. Therefore, almost half of the generated electric charge is collected into the storage node 3 via the depletion layer 4, and the remaining half is collected into the substrate 8 via the depletion layer 4a. Therefore, for example, if the secondary ion 2 penetrates into the storage node 3, the well 5 and the substrate 8, and consequently electric charge is collected into the storage node 3 where data “1” is stored, the data “1” stored in the storage node 3 is reversed to data “0” when the collected electric charge exceeds a certain amount (referred to as “critical charge”).
The principle of the soft errors caused by the cosmic ray neutrons is basically the same as the case of the alpha ray-induced soft errors. However, in the case where the soft errors are caused by a high energy neutron, it is principally different from the case of the alpha ray-induced error in the following points.
Difference 1:
Energy of generated secondary ions is high.
Difference 2:
Scattering directions of the secondary ions are isotropic.
Here, the above Difference 1 indicates that the electric charge amount generated within the semiconductor device is large, compared to the case of the alpha rays. Therefore, soft errors may easily occur in a semiconductor device in which the storage node 3 has a small critical charge. In addition, the above Difference 2 indicates a possibility that the secondary ions 2 may scatter into all the directions from the storage node 3. Therefore, a polyimide shielding (chip coating) conventionally used as a countermeasure against the alpha ray-induced soft errors is not sufficient as a countermeasure against the neutron-induced soft errors.
In the meantime, it is expected that finer structure and lower operational voltage of a semiconductor device will proceed further in the future without halt for the sake of achieving considerable increase in capacity and lower power consumption. However, as an obstacle in the move towards finer structure and lower operational voltage of the semiconductor device, an issue in terms of how to keep electrostatic capacitance held by the storage node in order to maintain the critical charge at a high level can be mentioned.
As the critical charge becomes smaller, resistivity against the soft errors caused by cosmic ray neutrons becomes lower. In view of this situation, a primary importance has conventionally been placed on keeping a certain critical charge high by enlarging the electrostatic capacitance of the storage node, and it is considered to be one of “common practices” in structural design of semiconductor device. As is well known, in DRAM, a condenser is made within a device, so as to keep electrostatic capacitance high. However, due to a decrease in cell area concurrent with the finer structure, a high conductivity material such as Ta2O5 is employed for the condenser. Employing such an expensive material and developing an adaptation process for the material have resulted in a high cost and spending manpower. In the case of SRAM, generally, a condenser is not made within the device, unlike the case of DRAM. Concurrent with finer structure of the device, the electrostatic capacitance of the storage node is kept decreased, and this situation leaves constraint on replacing material of interlayer insulation film to be a lower dielectric constant material.
On the other hand, since spacing between parasitic transistors becomes smaller as the structure becomes finer, a parasitic thyristor is turned on, thereby causing hard errors, which are reported as a way of example, such as latch up allowing a large current to flow, and SEGR (Single Event Gate Rupture) where the secondary ions remarkably increase an electrostatic field in the proximity of a gate oxide, resulting in a destroy of the oxide film. This may place a constraint on making a gate oxide film further thinner, which is required for finer structure and lower operational voltage of the semiconductor device.
Considering the problems above, it is important to evaluate errors caused by cosmic ray neutrons in a semiconductor device, and to reflect the evaluation result on designing the semiconductor device. Table 1 shows experimental methods to evaluate error resistivity of the semiconductor device.
TABLE 1CLASSIFICATION OFADVANTAGES/METHODSFEATURESDISADVANTAGESNEUTRONFIELDDevicePeriod forIRRADIATIONTESTINGresistivity candeviceMETHODbe directlyevaluation isevaluated.long.Obtainingdata from awide range andwith precisionis difficult.WHITESpectrum similarLimitedNEUTRONto that of cosmicfacility forMETHODray neutron isuse (e.g.used, and deviceLANSCE, RCNP).resistivity canbe evaluatedwithin a shortperiod.(QUASI-)(Quasi-)LimitedMONO-ENERGY)mono-energyfacility forNEUTRONneutron is used.use (e.g. TSL,METHODSpectrum ofTohoku Univ.cosmic rayCylic., RCNP).neutrons isLow fluxsuperimposed forTailintegration andcorrection isdevicenecessary.resistivity isevaluated.Usable as a basisfor a wide rangeof evaluation.PROTON IRRADIATIONDosimetry isEquivalencyMETHODeasier thanwith neutronneutron.irradiationhas not beenverified yet.HEAVY ION IRRADIATIONEvaluate a deviceOverallMETHODfor earthevaluation ofsatellitesecondary ionSuitable forincludingquantification ofunstableinfluence bynuclide is notindividualpossible.secondary ions
As shown in Table 1, there are experimental methods to evaluate error resistivity of semiconductor device, such as a neutron irradiation method to obtain an error rate by irradiating neutrons onto the semiconductor device, a proton irradiation method to obtain an error rate by irradiating protons instead of neutrons onto the semiconductor device, and a heavy ion irradiation method to obtain an error rate by irradiating heavy ions onto the semiconductor device, the heavy ions being generated by nuclear reaction between neutrons and atomic nuclei of the semiconductor device material.
Here, a general index to evaluate the error resistivity is called SEE (Single Event Effect) cross section (in the case of soft errors, it is called SEU (Single Event Upset) cross section). In general, it is defined by the following equation as a function of incident particle energy E.
                              σ          ⁡                      (            E            )                          =                                                            N                err                            ⁡                              (                E                )                                                                    ϕ                ⁡                                  (                  E                  )                                            ⁢                              T                irr                                              =                                                    N                err                            ⁡                              (                E                )                                                    ψ              ⁡                              (                E                )                                                                        [                  EQUATION          ⁢                                          ⁢          1                ]            
Here, Φ(E) denotes the number of neutrons incident to a unit area within a unit time (Flux), Tirr denotes an irradiating time, Ψ(E) denotes total number (Fluence) of neutrons incident to the unit area within the irradiating time Tirr, Nerr(E) denotes the number of errors occurred with respect to one device. Nerr(E) may also be defined as the number of errors occurred with respect to one bit. Here, σ(E) denotes the SEE cross section in which an error rate is expressed as an area, the error being generated by one neutron having energy E incident on the semiconductor device.
FIG. 15 shows a relationship between neutron energy (MeV) in a semiconductor device (SRAM) and SEE cross section (cm2). As understood from the graph indicated by the reference numeral 16, neutron energy E has a threshold value Eth in association with a threshold of nuclear spallation reaction. In other words, there is no possibility that an error in the semiconductor device occurs against a neutron having energy smaller than the threshold value Eth. Typically, the SEE cross section σ(E) is saturated with a value σ∞, which is in the higher energy side of the neutron energy E. It is to be noted that there is another report example where the SEE cross section is not saturated in the higher energy side of the neutron energy E, but it is rather reduced. Typically, the unit of flux Φ(E) is “number of incident particles/cm2/s”, and the unit of the fluence Ψ(E) is “number of incident particles/cm2. When the error rate SER (Single Event Error) in the environment, where the semiconductor device is actually used, is represented by a unit of FIT (Failure In Time), the SER is defined by the EQUATION 2 utilizing the SEE cross section σ(E). Here, when one error occurs every 109 hours, it is defined as “1 FIT”.
                              SER          ⁡                      (            FIT            )                          =                  3.6          ×                      10            12                    ⁢                                    ∫                              E                th                            ∞                        ⁢                                          σ                ⁡                                  (                  E                  )                                            ⁢                                                ⅆ                                      ϕ                    ⁡                                          (                      E                      )                                                                                        ⅆ                  E                                            ⁢                                                          ⁢                              ⅆ                E                                                                        [                  EQUATION          ⁢                                          ⁢          2                ]            
In the meantime, the proton irradiation method, as one of the above experimental methods to evaluate an error resistivity of the semiconductor device as shown in Table 1, is based on the premise that the proton and the neutron are a kind of twin particles being different only in isotopic spin, and the nuclear reaction for the two is physically equivalent except the Coulomb barrier. However, in practice, there is not much data showing that the proton and the neutron give the same error rate. Therefore, it is not possible to say that whether or not the error evaluation method using the proton is equivalent to the method using the neutron has already been verified. The heavy ion irradiation method is suitable for a physical mechanism study. However, when the neutrons and Si atomic nuclei, for example, are subjected to nuclear reaction, several dozen of nuclides are generated, including radioactive isotopes with a short life. Therefore, in fact, it is impossible to evaluate an actual error rate against the cosmic ray neutrons.
With the reasons as described above, it is thought that neutron irradiation method is suitable for evaluating an error rate of the semiconductor device caused by the cosmic ray neutrons. Here, as shown in Table 1, the neutron irradiation method is classified into field testing, white neutron method, (quasi-) mono-energy neutron method. The field testing is a method in which the semiconductor devices are placed on the ground to be operated thereon and errors caused by actual cosmic ray neutrons are directly measured. The white neutron method is a method which irradiates high-speed protons onto a tungsten block and the like, generates white neutrons having a spectrum with a shape analogous to a shape of cosmic ray neutron spectrum, and applies the white neutrons to the semiconductor device to measure errors (see International Electron Devices Meeting, San Francisco, Calif., Dec. 6-9, 1998, pp. 367-370 (1998), and Nuclear Science and Engineering, Vol. 106, pp. 208-218 (1990), which will be referred to as “Non-patent Documents 5 and 6”, respectively). The (quasi-) mono-energy neutron method is a method which irradiates high-speed protons to an Li plate, generates (quasi-) mono-energy neutrons, and measures errors by applying thus generated neutrons to the semiconductor device (for example, see International Conference on Information Technology and Application, Bathurst, No. 273-21 (2002), which will be referred to as “Non-patent Document 7).
The field testing as one of the neutron irradiation methods requires a period from at least half a year to one year or longer in order to obtain data statistically meaningful, even if around 1,000 units of semiconductor devices are used. In addition, cost for this method is expensive. Therefore, even if the field testing is necessary for simulation or verifying accelerating test, it is not practical to carry out this method for all the semiconductor devices prior to mass production thereof.
With the reasons as described above, it is thought that the white neutron method or the (quasi-) mono-energy neutron method is suitable for evaluating the error rate in the semiconductor device caused by the cosmic ray neutrons, those methods using neutrons outputted from an accelerator.